EP20K400GC655-3 vs EP20K400GI655-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-3 sa pamamagitan ng Intel at EP20K400GI655-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GC655-3 | EP20K400GI655-3 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20K | APEX 20KE |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 16640 | — |
| Total RAM Bits | 212992 | — |
| Number of Gates | 400000 | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | — |
| Temperature na Operasyon | -40C to +85C (industrial) | 0°C to 70°C (Industrial I grade) |
| Maximum Frequency | 167 MHz (per FPGAkey) | — |
| Process Technology | 0.22 um CMOS | CMOS, 2.5V core |
| Packhaging / Kaso | 655-BCPGA | — |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | — |
| Speed Grade | -3 (slowest grade in family) | -3 (slowest of the EP20K400 family) |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | Passive Serial, Passive Parallel Asynchronous, JTAG |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 (maximum) |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 4 |
| Number of Terminals | — | 655 |
| Packhaging | — | 655-Pin PGA (Plastic/CPGA, square) |
| JESD-30 Code | — | S-CPGA-P655 |
| Package Shape | — | Square |
| Form of Terminal | — | PIN/PEG (through-hole) |
| Uri ng Pagpapasok | — | Through-Hole (Socket) |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V or 3.3 V (MultiVolt I/O) |
| Embedded Memory | — | Dual-port RAM via Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |