EP20K400GC655-3X vs EP20K400GC655-2V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-3X sa pamamagitan ng Altera at EP20K400GC655-2V sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K400GC655-3X | EP20K400GC655-2V |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) | APEX 20KC (1.8 V, LVDS) |
| Manufacturer | Altera (now Intel FPGA) | — |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | ~400,000 (typical marketing figure) |
| Total RAM Bits | 212,992 bits | 212,992 |
| Maximum Internal Frequency | 167 MHz (speed grade -3) | — |
| Process Technology | 0.22 µm CMOS | CMOS, 0.18 um |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V (LVDS support per APEX 20KE datasheet) | — |
| Packhaging / Kaso | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) | — |
| Uri ng Pagpapasok | Through-Hole (CPGA, ceramic) | Through-hole (CPGA) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature grade] |
| Speed Grade | -3 (fastest) | -2 |
| Suffix Code | -X (extended / ceramic CPGA variant) | — |
| I/O Count | [DATA_NEEDED: max user I/O] | — |
| JTAG / Boundary Scan | IEEE 1149.1 (per APEX 20K family) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] | unknown |
| Logic Elements | — | 16,640 |
| Number of I/O | — | [DATA_NEEDED: I/O count] |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| Propagation Delay | — | 3.000 ns |
| LVDS Support | — | Yes |
| Packhaging | — | 655-CPGA (62.48 x 62.48 mm) |
| Package Type | — | Ceramic Pin Grid Array, through-hole |
| Lead-Free | — | unknown |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |