EP20K400GC655-3X vs EP20K400GC655-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-3X sa pamamagitan ng Altera at EP20K400GC655-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GC655-3X | EP20K400GC655-3 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) | APEX 20K |
| Manufacturer | Altera (now Intel FPGA) | Intel (formerly Altera) |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Total RAM Bits | 212,992 bits | 212992 |
| Maximum Internal Frequency | 167 MHz (speed grade -3) | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V (LVDS support per APEX 20KE datasheet) | — |
| Packhaging / Kaso | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) | 655-BCPGA |
| Uri ng Pagpapasok | Through-Hole (CPGA, ceramic) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Speed Grade | -3 (fastest) | -3 (slowest grade in family) |
| Suffix Code | -X (extended / ceramic CPGA variant) | — |
| I/O Count | [DATA_NEEDED: max user I/O] | — |
| JTAG / Boundary Scan | IEEE 1149.1 (per APEX 20K family) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] | [DATA_NEEDED: rohs status] |
| Logic Elements | — | 16640 |
| Number of Gates | — | 400000 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | — | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 167 MHz (per FPGAkey) |
| Supplier Device Package | — | 655-CPGA (62.48 x 62.48 mm) |
| Propagation Delay (tPD) | — | 3.6 ns (per Microchip USA listing) |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |
| Configuration Modes | — | Passive Serial, Passive Parallel Sync/Async, Active Serial |