EP20K400GI655-1X vs EP20K400GI655-2V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-1X sa pamamagitan ng Altera at EP20K400GI655-2V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400GI655-1X | EP20K400GI655-2V |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K |
| Device | EP20K400 | — |
| Logic Elements | 16640 | 16,640 |
| Number of Terminals | 655 | — |
| User I/O Lines | 502 | — |
| Dedicated Inputs | 4 | 6 |
| Package Type | Ceramic Pin Grid Array (CPGA) | — |
| Package Code (JESD-30) | S-CPGA-P655 | — |
| Package Equivalence Code | SPGA655,47X47 | SPGA655,47X47 |
| Package Body Material | CERAMIC (metal-sealed co-fired) | Ceramic |
| Speed Grade | -1 | — |
| Propagation Delay | 2.5 ns (typical for -1 grade) | 3.0 ns to 3.1 ns |
| Process Technology | CMOS, SRAM-based configuration | 0.18 µm CMOS |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 1 | 1 |
| Peak Reflow Temperature | 220 C | — |
| Temperature na Operasyon | -40 C to +85 C (industrial) | Industrial (per -2V speed grade) |
| Uri ng Pagpapasok | Through-Hole (PGA) | — |
| Tindminan RoHS | Compliant | Non-compliant (ceramic SPGA, contains lead) |
| Maximum Gates | — | 400,000 |
| Embedded RAM Bits | — | 212,992 |
| User I/O Pins | — | 496 |
| Packhaging | — | SPGA-655 (ceramic, 47 x 47 mm) |
| Core Supply Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | — | 3.3 V |