EP20K600CB652C7ES vs EP20K600CB652C-8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652C7ES sa pamamagitan ng Altera at EP20K600CB652C-8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CB652C7ES EP20K600CB652C-8
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20KC APEX 20KC (MultiCore)
Logic Elements 24,320 24,320
System Gates 600,000 —
Maximum System Gates 1,053,840 —
Embedded Memory Bits 311,296 —
Embedded System Blocks (ESB) 26 —
Maximum User I/O 488 —
User I/O (this package) 488 (652-BGA) —
Supply Voltage - Core 1.71 V to 1.89 V (1.8 V nominal) —
Maximum Internal Clock Frequency 1666.6 MHz —
Propagation Delay 1.6 ns 1.48 ns (per published source)
Process Technology 0.15 µm CMOS —
Temperature na Operasyon 0 °C to +85 °C (commercial) 0 C to 85 C (commercial)
Package Type 652-ball FineLine BGA —
JEDEC Package Code S-PBGA-B652 —
Configuration Modes Passive Serial, Passive Parallel, JTAG —
JTAG Boundary Scan IEEE 1149.1 compliant —
Tindminan RoHS [DATA_NEEDED: RoHS status] —
PLLs 4 —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (thermally enhanced)
Series — APEX 20KC
Typical Gates — 600,000
Embedded RAM — 311,296 bits
User I/Os — 488
Packhaging — 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch)
Speed Grade — -8 (slowest, most timing margin)
VCCIO Options — 1.8 V / 2.5 V / 3.3 V
Process — 0.15 µm all-layer copper metal
PCI Compliance — PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit
Memory Interface Support — DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS
Configuration — Enhanced (EPC) bitstream

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