EP20K600CB652I8 vs EP2A70B652C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652I8 sa pamamagitan ng Intel at EP2A70B652C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CB652I8 | EP2A70B652C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX II (Field-Programmable Gate Array) |
| Series | EP20K600 | APEX II |
| System Gates | 600,000 | — |
| Logic Elements / Cells | 24,320 | — |
| Maximum Operating Frequency | 301.21 MHz | — |
| Propagation Delay (tpd) | 1.78 ns (CMOS) | — |
| Process Technology | 0.15 µm CMOS | — |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | — |
| Packhaging | 652-ball FineLine BGA (S-PBGA-B652) | — |
| Package Code | BGA, square | — |
| Ball Pitch | 1.27 mm | — |
| Package Body Size | 45 mm × 45 mm | — |
| User I/O Lines | 488 | — |
| Dedicated Clock Inputs | 4 | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements (LEs) | — | 67200 |
| Typical Gates | — | 1140000 |
| Maximum User I/Os | — | 336 |
| Package Type | — | BGA-652 (FineLine BGA) |
| Package Size | — | 27 mm x 27 mm (approximate) |
| Operating Temperature Grade | — | Commercial (C) |
| Speed Grade | — | 7 |
| Core Voltage | — | 1.8 V |
| I/O Bank Voltage (VCCIO) | — | 1.5V / 1.8V / 2.5V / 3.3V (bank-dependent) |
| Configuration Interface | — | JTAG, Passive Serial |
| Uri ng Memory | — | Embedded SRAM blocks (ESBs) |
| PLL / Clock Management | — | Yes, dedicated PLL blocks |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |