EP20K600CB652I9N vs EP20K600CB652I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652I9N sa pamamagitan ng Altera at EP20K600CB652I7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K600CB652I9N - 600K APEX 20KC FPGA, 652-BGA, Industrial | Altera
EP20K600CB652I9N Obsolete
Pagsanggunian na paghahambing
| Parametro | EP20K600CB652I9N | EP20K600CB652I7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | — |
| System Gates | 600,000 | — |
| Maximum Operating Frequency | 250 MHz | 375.94 MHz |
| Process Technology | 0.15 um CMOS | 0.15 µm CMOS |
| Core Voltage | 1.8 V | — |
| I/O Voltage | 3.3 V | — |
| Total I/O Pins | 488 | — |
| General-Purpose I/O | 480 | — |
| Dedicated Inputs | 4 | — |
| Packhaging | 652-BGA (PBGA652) | 652-pin FineLine BGA |
| Terminal Pitch | 1.27 mm | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | — |
| Configuration Method | Passive Serial / Passive Parallel / JTAG | SRAM-based, JTAG (IEEE 1149.1) |
| Embedded Memory | ESB (Embedded System Block) RAM / CAM | — |
| I/O Standards | LVDS, PCI, LVTTL, LVCMOS | — |
| Typical Gates | — | 600,000 |
| Logic Elements (Cells) | — | 24,320 |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| User I/O Banks | — | [DATA_NEEDED: User I/O Banks] |
| Maximum User I/O | — | [DATA_NEEDED: Maximum User I/O] |
| Embedded System Block (ESB) Memory | — | 311,040 bits |
| Phase-Locked Loops (PLLs) | — | 4 |
| Operating Temperature Grade | — | Industrial (-40C to +100C) |
| Speed Grade | — | 7 |
| Tindminan RoHS | — | unknown |