EP20K600CB672C8 vs EP20K600CB652C9N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB672C8 sa pamamagitan ng Intel at EP20K600CB652C9N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K600CB672C8 - APEX 20KC FPGA 600K Gates 672-FBGA | Intel / Altera
EP20K600CB672C8 Obsolete
Pagsanggunian na paghahambing
| Parametro | EP20K600CB672C8 | EP20K600CB652C9N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX 20KC | — |
| Family | APEX-20KC® | APEX 20KC |
| Number of Logic Elements/Cells | 24320 | — |
| Total RAM Bits | 311296 | — |
| Number of I/O | 508 | — |
| Number of Gates | 600000 | — |
| Voltage - Supply | 1.71 V to 1.89 V (core); 3.0 V to 3.6 V (I/O) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0 C to 85 C (commercial) |
| Packhaging / Kaso | 672-BBGA, FCBGA (27 x 27 mm) | — |
| Supplier Device Package | 672-FBGA (27 x 27) | — |
| Speed Grade | C8 (approx. 301 MHz internal) | C9 (~1.48 ns propagation delay) |
| Process Technology | 0.15 µm CMOS | 0.15 micron all-layer copper CMOS |
| PLLs | 4 | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, GTL+, PCI 3.3 V | — |
| Tindminan RoHS | Unknown (legacy part, pre-RoHS era) | [DATA_NEEDED: rohs status] |
| Lead Free | Unknown | — |
| Device Type | — | Loadable PLD (FPGA) |
| Typical Gates | — | 600,000 |
| Logic Elements | — | 24,320 |
| Maximum User I/O | — | 488 |
| Packhaging | — | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) |
| Core Supply Voltage | — | 1.8 V |
| Architecture | — | MultiCore LUT + embedded system memory (ESB) |
| On-chip Memory | — | Embedded system memory blocks (dual-port RAM, FIFO) |
| Configuration Interface | — | JTAG (IEEE 1149.1) and serial/PROM configuration |
| Pin/Pin Compatibility | — | Pin-compatible with APEX 20KE devices of same package |
| Toolchain | — | Altera/Intel Quartus II (legacy APEX support) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |