EP20K600CB672C8N vs EP20K600CB672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB672C8N sa pamamagitan ng Intel at EP20K600CB672C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CB672C8N | EP20K600CB672C7 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX-20KC | APEX 20KC |
| Logic Elements (LEs) | 24,320 | — |
| Embedded Memory Bits | 311,296 | — |
| Maximum User I/O | 508 | — |
| Packhaging | 672-BBGA (FineLine BGA) | 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch) |
| Configuration Memory | SRAM, in-system programmable | — |
| Configuration Schemes | Passive Serial / Active Serial / JTAG (IEEE 1149.1) | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm all-layer copper-metal CMOS |
| Temperature na Operasyon | Commercial (0C to +85C) | 0 °C to 85 °C (commercial) |
| Speed Grade | C8 | C7 (commercial, 0 °C to 85 °C) |
| PCI Support | PCI-SIG compliant 3.3 V, 33/66 MHz, 32/64-bit | — |
| External Memory Interface | DDR SDRAM, ZBT SRAM | — |
| Dedicated Clock Inputs | 16 | — |
| PLLs | On-chip with clock-doubling and phase-shift | — |
| LVDS Channels | Up to 32 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Device Type | — | FPGA / Programmable Logic Device (PLD) |
| Typical Gates | — | 600,000 |
| Maximum System Gates | — | 1,053,840 |
| Logic Elements | — | 30,960 (typical) |
| Embedded Memory | — | 311 kbits (EAB-based) |
| User I/Os | — | 488 |
| Propagation Delay | — | 1.48 ns |
| Core Voltage | — | 2.5 V |
| I/O Voltage Support | — | 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O) |
| Number of PLLs | — | 4 |
| Dual-Port RAM | — | Yes (4.5 ns access) |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT |
| Configuration Method | — | EPC configuration devices / JTAG / passive serial |