EP20K600CB672C8N vs EP20K600CB672C7 比較
詳細並排比較 EP20K600CB672C8N 由 Intel 與 EP20K600CB672C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CB672C8N | EP20K600CB672C7 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX-20KC | APEX 20KC |
| Logic Elements (LEs) | 24,320 | — |
| Embedded Memory Bits | 311,296 | — |
| Maximum User I/O | 508 | — |
| 封裝 | 672-BBGA (FineLine BGA) | 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch) |
| Configuration Memory | SRAM, in-system programmable | — |
| Configuration Schemes | Passive Serial / Active Serial / JTAG (IEEE 1149.1) | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm all-layer copper-metal CMOS |
| 工作溫度 | Commercial (0C to +85C) | 0 °C to 85 °C (commercial) |
| Speed Grade | C8 | C7 (commercial, 0 °C to 85 °C) |
| PCI Support | PCI-SIG compliant 3.3 V, 33/66 MHz, 32/64-bit | — |
| External Memory Interface | DDR SDRAM, ZBT SRAM | — |
| Dedicated Clock Inputs | 16 | — |
| PLLs | On-chip with clock-doubling and phase-shift | — |
| LVDS Channels | Up to 32 | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| 安裝類型 | Surface Mount (BGA) | — |
| Device Type | — | FPGA / Programmable Logic Device (PLD) |
| Typical Gates | — | 600,000 |
| Maximum System Gates | — | 1,053,840 |
| Logic Elements | — | 30,960 (typical) |
| Embedded Memory | — | 311 kbits (EAB-based) |
| User I/Os | — | 488 |
| Propagation Delay | — | 1.48 ns |
| Core Voltage | — | 2.5 V |
| I/O Voltage Support | — | 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O) |
| Number of PLLs | — | 4 |
| Dual-Port RAM | — | Yes (4.5 ns access) |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT |
| Configuration Method | — | EPC configuration devices / JTAG / passive serial |