EP20K600CF672C7 vs EP20K600CB672C7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C7 sa pamamagitan ng Intel at EP20K600CB672C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672C7 EP20K600CB672C7
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX-20KC APEX 20KC
Device Type SPLD / FPGA FPGA / Programmable Logic Device (PLD)
System Gates 600,000 —
Logic Cells 24,320 —
User I/O 508 —
Packhaging 672-ball FC-FBGA (27x27 mm) 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch)
Ball Pitch 1.27 mm —
Core Voltage (VCCINT) 1.71 V to 1.89 V —
Process Technology 0.15 um CMOS, all-layer copper 0.15 µm all-layer copper-metal CMOS
Propagation Delay (typ.) 1.48 ns —
Temperature na Operasyon 0C to 85C (commercial) 0 °C to 85 °C (commercial)
Speed Grade C7 C7 (commercial, 0 °C to 85 °C)
Embedded Memory Dual-port RAM via ESBs 311 kbits (EAB-based)
CAM Support Yes (ESB-based content-addressable memory) —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS Compliant Compliant
Typical Gates — 600,000
Maximum System Gates — 1,053,840
Logic Elements — 30,960 (typical)
User I/Os — 488
Propagation Delay — 1.48 ns
Core Voltage — 2.5 V
I/O Voltage Support — 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O)
Number of PLLs — 4
Dual-Port RAM — Yes (4.5 ns access)
Supported I/O Standards — LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT
Configuration Method — EPC configuration devices / JTAG / passive serial

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