EP20K600CF672C7ES vs EP20K600CF672I-8ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C7ES sa pamamagitan ng Altera at EP20K600CF672I-8ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera
EP20K600CF672C7ES ⚠ Huling PagbiliAltera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES ObsoletePagsanggunian na paghahambing
| Parametro | EP20K600CF672C7ES | EP20K600CF672I-8ES |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX 20KC | — |
| Family | APEX 20K | APEX 20KC |
| Logic Elements / Cells | 24320 | — |
| System Gates | 600000 | — |
| Maximum User I/O | 504 | — |
| Maximum Input Lines | 508 | — |
| Number of Macrocells | 504 | — |
| Maximum Operating Frequency | 375.94 MHz (per FPGAkey listing) | — |
| Propagation Delay | 1.6 ns | — |
| Internal Reference Clock | 1666.6 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.18 micron CMOS SRAM |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| Package Type | FC-FBGA | — |
| Pin / Ball Count | 672 | — |
| Grade Suffix | ES (engineering sample / extended screening) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | -40C to +100C (Industrial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: moisture sensitivity level] |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (legacy Altera leaded BGA process) |
| Configuration Memory | SRAM-based (volatile) | — |
| Logic Elements | — | 24,320 |
| Typical Gates | — | 600,000 (ASIC-equivalent) |
| Embedded Memory Bits | — | 311,296 |
| Maximum User I/O Pins | — | 508 |
| Embedded PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Speed Grade | — | -8 (slower) |
| Packhaging | — | 672-ball BGA (FineLine BGA, 1.27 mm pitch) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG |
| In-System Programmability | — | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) |