EP20K600CF672C7ES vs EP20K600CF672I-8ES 比較

詳細並排比較 EP20K600CF672C7ES 由 Altera 與 EP20K600CF672I-8ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K600CF672C7ES EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera

EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera

EP20K600CF672C7ES ⚠ 最後購買機會

規格比較

參數 EP20K600CF672C7ES EP20K600CF672I-8ES
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Series APEX 20KC —
Family APEX 20K APEX 20KC
Logic Elements / Cells 24320 —
System Gates 600000 —
Maximum User I/O 504 —
Maximum Input Lines 508 —
Number of Macrocells 504 —
Maximum Operating Frequency 375.94 MHz (per FPGAkey listing) —
Propagation Delay 1.6 ns —
Internal Reference Clock 1666.6 MHz —
Process Technology 0.15 µm CMOS 0.18 micron CMOS SRAM
Core Supply Voltage (VCCINT) 1.8 V —
Package Type FC-FBGA —
Pin / Ball Count 672 —
Grade Suffix ES (engineering sample / extended screening) —
工作溫度 [DATA_NEEDED: operating temperature grade] -40C to +100C (Industrial)
安裝類型 Surface Mount (BGA) —
MSL 等級 [DATA_NEEDED: MSL rating] [DATA_NEEDED: moisture sensitivity level]
RoHS 狀態 [DATA_NEEDED: RoHS compliance] Non-compliant (legacy Altera leaded BGA process)
Configuration Memory SRAM-based (volatile) —
Logic Elements — 24,320
Typical Gates — 600,000 (ASIC-equivalent)
Embedded Memory Bits — 311,296
Maximum User I/O Pins — 508
Embedded PLLs — 4
Core Voltage — 1.8 V
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+
Speed Grade — -8 (slower)
封裝 — 672-ball BGA (FineLine BGA, 1.27 mm pitch)
Configuration Modes — Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG
In-System Programmability — Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1)

資料表與資源

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