EP20K600CF672C7N vs EP20K600CF672C7ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C7N sa pamamagitan ng Altera at EP20K600CF672C7ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP20K600CF672C7ES EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera

EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera

EP20K600CF672C7ES ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP20K600CF672C7N EP20K600CF672C7ES
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Device Family APEX 20KC —
Maximum System Gates 1,052,000 —
Typical Gates 600,000 —
Logic Elements / Cells 24,320 24320
Maximum User I/O Pins 488 —
Total Package Pins 652 —
Packhaging FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch —
Core Voltage 1.8 V —
Maximum Operating Frequency 375.94 MHz 375.94 MHz (per FPGAkey listing)
Propagation Delay 1.48 ns 1.6 ns
Process Technology 0.15 µm all-layer copper-metal CMOS 0.15 µm CMOS
Architecture MultiCore (LUT + Embedded System Memory) —
Temperature na Operasyon 0 °C to +85 °C (Commercial) [DATA_NEEDED: operating temperature grade]
Speed Grade C7 —
Seated Height 3.50 mm —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (BGA)
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance]
Series — APEX 20KC
Family — APEX 20K
System Gates — 600000
Maximum User I/O — 504
Maximum Input Lines — 508
Number of Macrocells — 504
Internal Reference Clock — 1666.6 MHz
Core Supply Voltage (VCCINT) — 1.8 V
Package Type — FC-FBGA
Pin / Ball Count — 672
Grade Suffix — ES (engineering sample / extended screening)
Level ng MSL — [DATA_NEEDED: MSL rating]
Configuration Memory — SRAM-based (volatile)

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