EP20K600CF672I7 vs EP20K600CF672I7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672I7 sa pamamagitan ng Altera at EP20K600CF672I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672I7 EP20K600CF672I7N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20KC APEX 20KC
Maximum Logic Elements 24,320 cells —
System Gates 600,000 —
Maximum User I/O 508 —
Maximum Internal Frequency 375.94 MHz 376 MHz
Process Technology 0.15 µm CMOS —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 3.3 V (LVTTL/LVCMOS compatible) —
Speed Grade -7 I7 (-40 °C to +100 °C industrial)
Temperature na Operasyon -40 °C to +100 °C (industrial, I-suffix) —
Packhaging 672-ball FineLine BGA (FC-FBGA, 27×27 mm) 672-ball FineLine BGA (FC-FBGA)
Ball Pitch 1.00 mm 1.0 mm
Embedded System Blocks Yes (dual-port RAM / CAM) —
Configuration Interface IEEE 1149.1 JTAG, passive serial, fast passive parallel —
Uri ng Pagpapasok Surface Mount (BGA) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Technology — 0.15 µm CMOS
Maximum System Gates — 600,000
Logic Elements — 24,320
Maximum User I/O Pins — 508
Embedded System Blocks (ESBs) — 160
Total Embedded RAM (max) — 311,296 bits
Core Voltage (VCCINT) — 1.8 V
I/O Voltage (VCCIO) — 2.5 V / 3.3 V (MultiVolt, bank-dependent)
Package Body Size — 27 mm × 27 mm
Propagation Delay (typical) — 1.6 ns
Configuration Method — JTAG (IEEE 1149.1) + EPC configuration device
Lead-Free Finish (N suffix) — Yes

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