EP20K600CF672I7N vs EP20K600CF672I6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672I7N sa pamamagitan ng Intel at EP20K600CF672I6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CF672I7N | EP20K600CF672I6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O Pins | 508 | 508 |
| Maximum Internal Frequency | 376 MHz | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | — |
| Packhaging | 672-ball FineLine BGA (FC-FBGA) | 672-BGA FineLine BGA |
| Ball Pitch | 1.0 mm | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | CF |
| Propagation Delay (typical) | 1.6 ns | — |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | SRAM (volatile) |
| Lead-Free Finish (N suffix) | Yes | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Device | — | EP20K600 |
| Typical Gates | — | 600,000 |
| Embedded Memory Bits | — | 311,296 |
| Number of PLLs | — | 4 |
| Temperature Grade | — | Industrial (I) |
| Temperature na Operasyon | — | -40C to +85C |
| Process Technology | — | 0.18 micron CMOS |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |