EP20K600CF672I8 vs EP20K600CF672I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672I8 sa pamamagitan ng Altera at EP20K600CF672I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CF672I8 | EP20K600CF672I7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Device Type | SPLD / FPGA | — |
| Logic Elements / Cells | 24,320 | — |
| Macros (Logic Cells) | 2432 | — |
| Typical Gate Count | 600,000 gates | — |
| Embedded Memory | 311,296 bits | — |
| User I/Os | 488 to 508 | — |
| Bilang ng Pins | 652 (functional) / 672 (BGA balls) | — |
| Propagation Delay (typical) | 1.48 ns | 1.6 ns |
| Internal Frequency (max) | [DATA_NEEDED: max internal frequency in MHz] | — |
| Core Supply Voltage | 1.8 V | — |
| Process Technology | 0.15 µm all-layer copper | — |
| Temperature na Operasyon | 0 °C to +85 °C (Industrial) | — |
| Package Type | 672-ball BGA, 45 x 45 mm, 1.27 mm pitch | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Compliant per legacy product records | [DATA_NEEDED: RoHS compliance] |
| Configuration Interface | JTAG / Passive Serial | — |
| Design Tool | Quartus II (legacy MAX+PLUS II) | — |
| Technology | — | 0.15 µm CMOS |
| Maximum System Gates | — | 600,000 |
| Logic Elements | — | 24,320 |
| Maximum User I/O Pins | — | 508 |
| Maximum Internal Frequency | — | 376 MHz |
| Embedded System Blocks (ESBs) | — | 160 |
| Total Embedded RAM (max) | — | 311,296 bits |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V (MultiVolt, bank-dependent) |
| Packhaging | — | 672-ball FineLine BGA (FC-FBGA) |
| Ball Pitch | — | 1.0 mm |
| Package Body Size | — | 27 mm × 27 mm |
| Speed Grade | — | I7 (-40 °C to +100 °C industrial) |
| Configuration Method | — | JTAG (IEEE 1149.1) + EPC configuration device |
| Lead-Free Finish (N suffix) | — | Yes |