EP20K600CF672I8N vs EP20K600CF672I8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672I8N sa pamamagitan ng Intel at EP20K600CF672I8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672I8N EP20K600CF672I8
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family APEX 20KC —
Device Type SPLD / PLD (FPGA-class) SPLD / FPGA
System Gates 600K —
Logic Elements / Cells 24,320 24,320
Maximum User I/O (digchip) 488 —
Maximum User I/O (Altera) 508 —
Total Package Pins 672 —
Package Type FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch 672-ball BGA, 45 x 45 mm, 1.27 mm pitch
Internal Performance 301.21 MHz —
Propagation Delay 1.48 ns —
Core Supply Voltage 1.8 V 1.8 V
Process Technology 0.15-um all-layer copper-metal 0.15 µm all-layer copper
Temperature na Operasyon 0C to 85C (Industrial) 0 °C to +85 °C (Industrial)
Pin-Compatible With APEX 20KE family —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] Compliant per legacy product records
Family — APEX 20KC
Macros (Logic Cells) — 2432
Typical Gate Count — 600,000 gates
Embedded Memory — 311,296 bits
User I/Os — 488 to 508
Bilang ng Pins — 652 (functional) / 672 (BGA balls)
Propagation Delay (typical) — 1.48 ns
Internal Frequency (max) — [DATA_NEEDED: max internal frequency in MHz]
Uri ng Pagpapasok — Surface Mount
Configuration Interface — JTAG / Passive Serial
Design Tool — Quartus II (legacy MAX+PLUS II)

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