EP20K600CF672I8N vs EP20K600CF672I8 比較
詳細並排比較 EP20K600CF672I8N 由 Intel 與 EP20K600CF672I8 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CF672I8N | EP20K600CF672I8 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | APEX 20KC | — |
| Device Type | SPLD / PLD (FPGA-class) | SPLD / FPGA |
| System Gates | 600K | — |
| Logic Elements / Cells | 24,320 | 24,320 |
| Maximum User I/O (digchip) | 488 | — |
| Maximum User I/O (Altera) | 508 | — |
| Total Package Pins | 672 | — |
| Package Type | FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch | 672-ball BGA, 45 x 45 mm, 1.27 mm pitch |
| Internal Performance | 301.21 MHz | — |
| Propagation Delay | 1.48 ns | — |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Process Technology | 0.15-um all-layer copper-metal | 0.15 µm all-layer copper |
| 工作溫度 | 0C to 85C (Industrial) | 0 °C to +85 °C (Industrial) |
| Pin-Compatible With | APEX 20KE family | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | Compliant per legacy product records |
| Family | — | APEX 20KC |
| Macros (Logic Cells) | — | 2432 |
| Typical Gate Count | — | 600,000 gates |
| Embedded Memory | — | 311,296 bits |
| User I/Os | — | 488 to 508 |
| 腳位數 | — | 652 (functional) / 672 (BGA balls) |
| Propagation Delay (typical) | — | 1.48 ns |
| Internal Frequency (max) | — | [DATA_NEEDED: max internal frequency in MHz] |
| 安裝類型 | — | Surface Mount |
| Configuration Interface | — | JTAG / Passive Serial |
| Design Tool | — | Quartus II (legacy MAX+PLUS II) |