EP20K600EBC652-2X vs EP20K600EFC144-2XN Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600EBC652-2X sa pamamagitan ng Altera at EP20K600EFC144-2XN sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600EBC652-2X EP20K600EFC144-2XN
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family APEX 20KE —
Device Type SPLD / FPGA (Field Programmable Gate Array) —
Logic Elements (LEs) 24,320 —
Macros 24,320 —
Embedded Memory Bits 311,296 bits —
User I/Os 488 —
Packhaging 652-ball BGA, 45 x 45 mm, 1.27 mm pitch 144-ball FineLine BGA
Total Pins / Balls 652 —
Propagation Delay 1.48 ns —
Temperature na Operasyon 0 °C to +85 °C (commercial) -40C to +85C (industrial, 'N' suffix)
Process Technology 0.15 µm all-layer copper CMOS 0.18 um CMOS, 6-layer metal
Core Supply Voltage 2.5 V —
I/O Standard Support LVTTL, LVCMOS, PCI, SSTL, GTL+ —
Configuration Modes Passive serial, passive parallel, JTAG (IEEE 1149.1) —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS]
Family — APEX 20KE
Logic Elements — 24,576
Typical Gates — 600,000
Maximum System Gates — 1,053,840
Embedded RAM Bits — 311,040 bits (~38 KB)
Number of ESBs (Embedded System Blocks) — [DATA_NEEDED: ESB count]
Number of Multiplier Blocks — [DATA_NEEDED: multiplier count]
Number of PLLs — 4
Number of I/O Pins — [DATA_NEEDED: usable I/O count]
Core Voltage — 1.8 V
I/O Voltage Banks — Multi-voltage (LVTTL/LVCMOS/PCI)
Speed Grade — -2 (mid-tier)
Configuration Method — SRAM, IEEE 1532 / passive serial / passive parallel

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