EP20K600EBC652-3 vs EP2A15B652C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600EBC652-3 sa pamamagitan ng Intel at EP2A15B652C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600EBC652-3 | EP2A15B652C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KE | — |
| Family | APEX 20K | APEX II |
| Device Type | FPGA (Field Programmable Gate Array) / SPLD Loadable | — |
| Logic Elements | 24320 | 30000 (approx) |
| Embedded Memory | 311296 bits | — |
| User I/Os | 488 | — |
| Number of Terminals | 652 | — |
| Package Type | BGA-652 (45 x 45 mm, 1.27 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Propagation Delay | 1.48 ns | — |
| Temperature na Operasyon | 0 C to 85 C | 0C to +85C (commercial, suffix C7) |
| Speed Grade | -3 | -7 |
| Process Technology | 0.15-micron all-layer copper CMOS | 0.18 micron CMOS |
| Core Voltage | [DATA_NEEDED: core voltage] | — |
| I/O Voltage Support | Multi-volt 3.3 V / 2.5 V / 1.8 V | — |
| Configuration Method | JTAG / serial / passive parallel | SRAM-based, requires external configuration memory |
| PLLs | 4 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - legacy APEX II family] |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Typical Gates | — | 1.5 million |
| Maximum User I/O Pins | — | [DATA_NEEDED: exact user I/O count] |
| Embedded System Blocks (ESB) | — | Yes - configurable as RAM/ROM or product-term logic |
| Supply Voltage - Core | — | [DATA_NEEDED: VCCINT voltage] |
| Supply Voltage - I/O | — | [DATA_NEEDED: VCCIO voltage] |
| Packhaging | — | 652-ball BGA |
| Hot Socketing Support | — | Yes (MultiCore hot-socketing) |
| Design Tool | — | Quartus II (legacy) |