EP2A25F672I-9 vs EP2A25F672C7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A25F672I-9 sa pamamagitan ng Intel at EP2A25F672C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A25F672I-9 EP2A25F672C7
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family APEX II —
Logic Elements (typical) 25,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] 1,650,000
Embedded System Blocks (ESB) Memory 1,125 Kbits —
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O pins] —
Number of PLLs 4 —
Process Technology 0.18 µm CMOS 0.15-um all-layer copper, up to 8 metal layers
Core Voltage 1.5 V / 1.8 V (speed-grade dependent) —
Operating Temperature Grade Industrial (-40 °C to +100 °C junction) —
Speed Grade -9 -7
Packhaging 672-pin FCBGA (FineLine BGA) 672-ball FCBGA (FineLine BGA)
Uri ng Pagpapasok Surface Mount (BGA) —
Level ng Sensitivity sa Asid ng Moisture (MSL) 3 (per Vyrian listing) —
Peak Reflow Temperature 220 °C (per Vyrian listing) —
Configuration Method JTAG / serial configuration EPROM —
Supported I/O Standards LVTTL, LVCMOS, LVDS, PCI —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Legacy Status Obsolete - consult Altera / Intel FPGA archive for documentation —
Product Family — APEX II
Logic Elements — 25,000
Maximum RAM Bits — 422,976
User I/O Count — 492
Supply Voltage (Core) — 1.5 V
LVDS Data Rate — 1 Gbps per channel (True-LVDS)
I/O Standards Supported — LVDS, LVPECL, PCML, HyperTransport
Temperature na Operasyon — 0C to +85C (Commercial)
Configuration Mode — Passive Serial, Passive Parallel, JTAG
Embedded System Blocks (ESB) — Yes - RAM, ROM, CAM, multiplier support

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