EP2A40F1020C8N vs EP2A40F1020I9 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F1020C8N sa pamamagitan ng Intel at EP2A40F1020I9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F1020C8N | EP2A40F1020I9 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | APEX II | — |
| Logic Technology | CMOS | — |
| Logic Gates | 1.5 million | — |
| Logic Cells | 38,400 | 38,400 |
| Nominal Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| User I/Os | 735 | — |
| Package Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA, BGA-1020 | — |
| Package Body Size | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | — |
| Reported Operating Frequency | 376 MHz | — |
| Alternative Reported Frequency | 562 MHz | — |
| Reported Propagation Delay | 1.78 ns | — |
| Alternative Reported Propagation Delay | 1.55 ns | — |
| Fabrication Process | 0.15 µm | — |
| Maximum Reported Metal Layers | 8 layers | — |
| Temperature na Operasyon | 0 °C to 85 °C | [DATA_NEEDED: junction temperature range for I9 grade] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Terminal Form | Ball | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: confirm RoHS compliance for FC-FBGA] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX II |
| Series | — | EP2A |
| System Gates | — | 1.5 M |
| Maximum Operating Frequency | — | 366 MHz |
| Process Technology | — | 0.15 µm |
| Core Voltage | — | 1.5 V |
| Packhaging | — | 1020-pin FC-FBGA |
| Bilang ng Pin | — | 1020 |
| Temperature Grade | — | Industrial (I9) |
| Logic Element Type | — | 4-input LUT |
| Embedded Memory | — | ESBs (dual-port RAM / ROM / FIFO) |
| Configuration Method | — | JTAG / passive serial / passive parallel |