EP2A40F1020C9ES vs EP2A40F1020C7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F1020C9ES sa pamamagitan ng Altera at EP2A40F1020C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F1020C9ES EP2A40F1020C7N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX II APEX II
System Gates 1.5 M 1,500,000 (1.5 M)
Logic Cells / Elements 38,400 —
Maximum Internal Clock Frequency 366 MHz —
Process Technology 0.15 µm CMOS —
Core Supply Voltage 1.5 V 1.5 V nominal (1.425 V – 1.575 V)
Packhaging 1020-pin FC-FBGA FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line
Package Type Flip-Chip Fine-Pitch Ball Grid Array —
Uri ng Pagpapasok Surface Mount Surface Mount
Embedded Memory Embedded System Blocks (ESBs) - RAM/ROM ESB-based, 504 Kbits total
I/O Standards LVDS and other high-speed standards (per family datasheet) —
RAM Support Synchronous and asynchronous —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] 0 °C to +85 °C (commercial, C7 grade)
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Technology — 0.15 µm all-layer copper CMOS, up to 8 metal layers
Logic Elements — 38,400
Maximum Internal Performance — 562 MHz
Propagation Delay — 1.55 ns
User I/O Pins — 735
PLLs — 4
Clock Networks — 12
True-LVDS Data Rate — 1 Gbps
Supported I/O Standards — True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL
Logic Family — CMOS
Terminal Form — BGA ball (flip-chip)

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