EP2A40F1020I9N vs EP2A40F1020C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F1020I9N sa pamamagitan ng Intel at EP2A40F1020C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2A40F1020C7N - APEX II 1.5M Gates FPGA, 735 I/O, FC-FBGA-1020 | Intel
EP2A40F1020C7N ObsoletePagsanggunian na paghahambing
| Parametro | EP2A40F1020I9N | EP2A40F1020C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Device Logic Elements / Cells | 38,400 cells | — |
| System Gates | 1,500,000 (1.5 M) | 1,500,000 (1.5 M) |
| Maximum Operating Frequency | 366 MHz | — |
| Process Technology | 0.15 um CMOS, up to 8 metal layers | — |
| Core Supply Voltage | 1.5 V | 1.5 V nominal (1.425 V – 1.575 V) |
| User I/O Count | 735 bidirectional I/O | — |
| Packhaging | 1020-pin FC-FBGA (Flip-Chip FineLine BGA) | FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line |
| Operating Temperature Grade | Industrial (I9 suffix: -40C to +100C per Altera APEX II convention) | — |
| High-Speed I/O Standards | True-LVDS (up to 1 Gbps), LVPECL, PCML, HyperTransport | — |
| Embedded Memory | ESB-based True-Dual-Port/Single-Port RAM, ROM, CAM (bits [DATA_NEEDED: total RAM bits]) | ESB-based, 504 Kbits total |
| Clock Management | PLLs (count [DATA_NEEDED: PLL count]) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous/Synchronous, JTAG | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Katayuan ng Lifecycle | Obsolete (per distributor listings / Altera APEX II family EOL) | — |
| Technology | — | 0.15 µm all-layer copper CMOS, up to 8 metal layers |
| Logic Elements | — | 38,400 |
| Maximum Internal Performance | — | 562 MHz |
| Propagation Delay | — | 1.55 ns |
| User I/O Pins | — | 735 |
| PLLs | — | 4 |
| Clock Networks | — | 12 |
| True-LVDS Data Rate | — | 1 Gbps |
| Supported I/O Standards | — | True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL |
| Logic Family | — | CMOS |
| Temperature na Operasyon | — | 0 °C to +85 °C (commercial, C7 grade) |
| Terminal Form | — | BGA ball (flip-chip) |