EP2A40F672C6N vs EP2A40F1020C7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C6N sa pamamagitan ng Intel at EP2A40F1020C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F672C6N EP2A40F1020C7N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX II APEX II
Logic Elements 40,000 38,400
Maximum System Gates 1,125,000 —
Embedded RAM Bits 442,368 —
Embedded System Blocks (ESBs) 160 —
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O count] —
Core Voltage 1.5 V —
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V —
Packhaging 672-ball FineLine BGA FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line
Temperature na Operasyon Commercial (0C to +85C) 0 °C to +85 °C (commercial, C7 grade)
Speed Grade C6 (per part number suffix) —
Configuration Methods Passive Serial, Passive Parallel, JTAG —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] —
Process Technology SRAM-based, 0.18 um (per family datasheet) —
PLL Count [DATA_NEEDED: PLL count] —
Technology — 0.15 µm all-layer copper CMOS, up to 8 metal layers
System Gates — 1,500,000 (1.5 M)
Embedded Memory — ESB-based, 504 Kbits total
Maximum Internal Performance — 562 MHz
Propagation Delay — 1.55 ns
User I/O Pins — 735
PLLs — 4
Clock Networks — 12
True-LVDS Data Rate — 1 Gbps
Supported I/O Standards — True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL
Core Supply Voltage — 1.5 V nominal (1.425 V – 1.575 V)
Logic Family — CMOS
Terminal Form — BGA ball (flip-chip)

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