EP2A40F672C6N vs EP2A40F1020C7N 比較
詳細並排比較 EP2A40F672C6N 由 Intel 與 EP2A40F1020C7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP2A40F1020C7N - APEX II 1.5M Gates FPGA, 735 I/O, FC-FBGA-1020 | Intel
EP2A40F1020C7N Obsolete規格比較
| 參數 | EP2A40F672C6N | EP2A40F1020C7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38,400 |
| Maximum System Gates | 1,125,000 | — |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Core Voltage | 1.5 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| 封裝 | 672-ball FineLine BGA | FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line |
| 工作溫度 | Commercial (0C to +85C) | 0 °C to +85 °C (commercial, C7 grade) |
| Speed Grade | C6 (per part number suffix) | — |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | — |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | — |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Technology | — | 0.15 µm all-layer copper CMOS, up to 8 metal layers |
| System Gates | — | 1,500,000 (1.5 M) |
| Embedded Memory | — | ESB-based, 504 Kbits total |
| Maximum Internal Performance | — | 562 MHz |
| Propagation Delay | — | 1.55 ns |
| User I/O Pins | — | 735 |
| PLLs | — | 4 |
| Clock Networks | — | 12 |
| True-LVDS Data Rate | — | 1 Gbps |
| Supported I/O Standards | — | True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL |
| Core Supply Voltage | — | 1.5 V nominal (1.425 V – 1.575 V) |
| Logic Family | — | CMOS |
| Terminal Form | — | BGA ball (flip-chip) |