EP2A40F672C6N vs EP2A40F672C9ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C6N sa pamamagitan ng Intel at EP2A40F672C9ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F672C6N | EP2A40F672C9ES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38,400 |
| Maximum System Gates | 1,125,000 | — |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Core Voltage | 1.5 V | 1.5 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| Packhaging | 672-ball FineLine BGA | 672-pin FC-FBGA |
| Temperature na Operasyon | Commercial (0C to +85C) | — |
| Speed Grade | C6 (per part number suffix) | -9 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 µm CMOS |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| System Gates | — | 1,500,000 |
| Maximum User I/O | — | 492 |
| Operating Frequency (max) | — | 366 MHz |
| Configuration Modes | — | PS, PPS, PPA, JTAG, FPP |
| Embedded Memory (ESB) | — | Yes (RAM/ROM/CAM) |
| I/O Standards | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |