EP2A40F672C8 vs EP2A40F672C9 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C8 sa pamamagitan ng Intel at EP2A40F672C9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera
EP2A40F672C9 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2A40F672C8 | EP2A40F672C9 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX II | APEX II |
| Logic Family | CMOS | CMOS |
| Typical Logic Elements (LEs) | 40,000 | — |
| Embedded Memory | Up to 1.5 Mbits | — |
| User I/Os | 492 pins | 492 |
| Bilang ng Pins | 672 | 672 |
| Package Type | FineLine BGA, 27 x 27 mm, 1.0 mm pitch | — |
| Process Technology | 0.15-micron all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Propagation Delay (speed grade C8) | 1.55 ns | — |
| Temperature na Operasyon | 0 C to 85 C (commercial) | 0 °C to 85 °C (commercial) |
| Phase-Locked Loops (PLLs) | 4 | — |
| LVDS Signaling Support | Up to 1 Gbps | — |
| Multipliers | Embedded multiplier blocks | — |
| I/O Standards | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Device Family | — | APEX II PLD |
| Logic Elements / Cells | — | 38,400 |
| System Gates | — | 1.5 M |
| Macros | — | 2,560 |
| Packhaging | — | 672-BBGA, FC-FBGA (FineLine) |
| Package Size | — | 27 mm × 27 mm, 1 mm ball pitch |
| Core Voltage | — | 1.5 V |
| Propagation Delay | — | 1.55 ns |
| Internal Speed Grade | — | 366 MHz |
| I/O Standards Supported | — | True-LVDS, LVPECL, PCML, HyperTransport |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |