EP2A40F672C8 vs EP2A40F672C9 比較

詳細並排比較 EP2A40F672C8 由 Intel 與 EP2A40F672C9 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP2A40F672C9 EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 ⚠ 最後購買機會

規格比較

參數 EP2A40F672C8 EP2A40F672C9
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 最後購買
Family APEX II APEX II
Logic Family CMOS CMOS
Typical Logic Elements (LEs) 40,000 —
Embedded Memory Up to 1.5 Mbits —
User I/Os 492 pins 492
腳位數 672 672
Package Type FineLine BGA, 27 x 27 mm, 1.0 mm pitch —
Process Technology 0.15-micron all-layer copper, up to 8 metal layers 0.15 µm all-layer copper, up to 8 metal layers
Propagation Delay (speed grade C8) 1.55 ns —
工作溫度 0 C to 85 C (commercial) 0 °C to 85 °C (commercial)
Phase-Locked Loops (PLLs) 4 —
LVDS Signaling Support Up to 1 Gbps —
Multipliers Embedded multiplier blocks —
I/O Standards LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS —
安裝類型 Surface Mount (BGA) Surface Mount
Device Family — APEX II PLD
Logic Elements / Cells — 38,400
System Gates — 1.5 M
Macros — 2,560
封裝 — 672-BBGA, FC-FBGA (FineLine)
Package Size — 27 mm × 27 mm, 1 mm ball pitch
Core Voltage — 1.5 V
Propagation Delay — 1.55 ns
Internal Speed Grade — 366 MHz
I/O Standards Supported — True-LVDS, LVPECL, PCML, HyperTransport
RoHS 狀態 — [DATA_NEEDED: RoHS status]

資料表與資源

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