EP2A40F672C8N vs EP2A40F672C9 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C8N sa pamamagitan ng Intel at EP2A40F672C9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F672C8N EP2A40F672C9
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family APEX II APEX II
Series EP2A40 —
Logic Family CMOS CMOS
System Gates 1.5 M 1.5 M
Logic Elements / Cells 38,400 38,400
Maximum Operating Frequency 376 MHz —
Propagation Delay 1.55 ns 1.55 ns
Technology Node 0.15 µm —
Process Feature All-layer copper, up to 8 metal layers —
Nominal Supply Voltage (VCCINT) 1.5 V —
Supply Voltage Range 1.425 V to 1.575 V —
User I/Os 492 492
Number of Pins / Balls 672 —
Package Type FC-FBGA (FineLine BGA) —
Package Dimensions 27 x 27 mm —
Ball Pitch 1.0 mm —
LVDS Data Rate 1 Gbps —
Embedded PLLs 4 —
Programming Interface JTAG (IEEE 1149.1) —
Operating Temperature (Commercial) 0 °C to 85 °C —
Speed Grade C8 —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family — APEX II PLD
Macros — 2,560
Bilang ng Pins — 672
Packhaging — 672-BBGA, FC-FBGA (FineLine)
Package Size — 27 mm × 27 mm, 1 mm ball pitch
Core Voltage — 1.5 V
Process Technology — 0.15 µm all-layer copper, up to 8 metal layers
Internal Speed Grade — 366 MHz
Temperature na Operasyon — 0 °C to 85 °C (commercial)
I/O Standards Supported — True-LVDS, LVPECL, PCML, HyperTransport
Uri ng Pagpapasok — Surface Mount

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