EP2A40F672I7N vs EP2A40F672C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672I7N sa pamamagitan ng Intel at EP2A40F672C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F672I7N | EP2A40F672C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| System Gates | 1.5 M | — |
| Logic Cells / Elements | 38,400 | — |
| Macrocells | 16 | — |
| Product Terms per Macrocell | 32 | — |
| Maximum Internal Frequency | 562 MHz | — |
| Propagation Delay (PLA mode) | 1.55 ns | — |
| User I/O Lines | 492 | — |
| Core Voltage | 1.5 V | 1.5 V |
| Process Technology | 0.15 µm | SRAM-based, 0.18 um (per family datasheet) |
| Packhaging | 672-pin FC-FBGA | 672-ball FineLine BGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | Commercial (0C to +85C) |
| Tindminan RoHS | Compliant (Pb-free) | [DATA_NEEDED: RoHS compliance status] |
| Configuration Interface | JTAG, Passive Serial, Passive Parallel, Synchronous | — |
| Logic Elements | — | 40,000 |
| Maximum System Gates | — | 1,125,000 |
| Embedded RAM Bits | — | 442,368 |
| Embedded System Blocks (ESBs) | — | 160 |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V |
| Speed Grade | — | C6 (per part number suffix) |
| Configuration Methods | — | Passive Serial, Passive Parallel, JTAG |
| PLL Count | — | [DATA_NEEDED: PLL count] |