EP2A70B724I9 vs EP2A70B724I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A70B724I9 sa pamamagitan ng Altera at EP2A70B724I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2A70B724I7 - APEX II FPGA 3M Gates 67200 Cells 420MHz 1.5V 724-FCBGA | Intel
EP2A70B724I7 ObsoletePagsanggunian na paghahambing
| Parametro | EP2A70B724I9 | EP2A70B724I7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 67,200 | 67200 |
| System Gates | Approximately 3,000,000 | — |
| Embedded Memory | 540 Kbits (1,146,880 bits total ESB memory per Jotrin listing) | [DATA_NEEDED: ESB bits - 429 Kb or similar] |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Operating Frequency | 198 MHz | — |
| Number of PLLs | 4 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Packhaging | 724-pin FCBGA (Flip-Chip BGA) | 724-pin FCBGA (FineLine BGA) |
| Operating Temperature Grade | Industrial (-40C to +100C) | Industrial (-40 C to +100 C case) |
| Uri ng Pagpapasok | Surface Mount | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Configuration Mode | SRAM-based, configurable via JTAG or EPC enhanced configuration devices | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not stated in provided data] |
| Manufacturer | — | Intel (formerly Altera) |
| Maximum System Gates | — | 3 M |
| Maximum User I/O Pins | — | approximately 422 (724-pin FCBGA) |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltages Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| PLL Blocks | — | 4 |
| True-LVDS Channels | — | 8 |
| Maximum Internal Frequency | — | 420 MHz |
| Configuration Interface | — | JTAG (IEEE 1149.1) / IEEE 1532 ISP |