EP2A70B724I9 vs EP2A70B724I7 比較
詳細並排比較 EP2A70B724I9 由 Altera 與 EP2A70B724I7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP2A70B724I7 - APEX II FPGA 3M Gates 67200 Cells 420MHz 1.5V 724-FCBGA | Intel
EP2A70B724I7 Obsolete規格比較
| 參數 | EP2A70B724I9 | EP2A70B724I7 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 67,200 | 67200 |
| System Gates | Approximately 3,000,000 | — |
| Embedded Memory | 540 Kbits (1,146,880 bits total ESB memory per Jotrin listing) | [DATA_NEEDED: ESB bits - 429 Kb or similar] |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Operating Frequency | 198 MHz | — |
| Number of PLLs | 4 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| 封裝 | 724-pin FCBGA (Flip-Chip BGA) | 724-pin FCBGA (FineLine BGA) |
| Operating Temperature Grade | Industrial (-40C to +100C) | Industrial (-40 C to +100 C case) |
| 安裝類型 | Surface Mount | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Configuration Mode | SRAM-based, configurable via JTAG or EPC enhanced configuration devices | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not stated in provided data] |
| Manufacturer | — | Intel (formerly Altera) |
| Maximum System Gates | — | 3 M |
| Maximum User I/O Pins | — | approximately 422 (724-pin FCBGA) |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltages Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| PLL Blocks | — | 4 |
| True-LVDS Channels | — | 8 |
| Maximum Internal Frequency | — | 420 MHz |
| Configuration Interface | — | JTAG (IEEE 1149.1) / IEEE 1532 ISP |