EP2C35F672C7 vs EP2C50F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2C35F672C7 sa pamamagitan ng Intel at EP2C50F672C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2C50F672C7 - Cyclone II FPGA, 50K LE, 672-FBGA | Intel / Altera
EP2C50F672C7 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2C35F672C7 | EP2C50F672C7 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Series | Cyclone II | — |
| Logic Elements (LE) | 33,216 | 50,528 |
| Embedded Memory Bits | 483,840 bits (105 M4K blocks) | 594,432 bits |
| User I/O Count | 475 | — |
| Embedded 18x18 Multipliers | 35 | 86 (150 per device family datasheet figure) |
| PLLs | 4 | — |
| Packhaging | 672-BGA (FineLine BGA) | 672-ball FineLine BGA (FBGA-672) |
| Speed Grade | 7 (commercial) | -7 |
| Process Technology | 90 nm low-k CMOS | 90 nm CMOS with low-k dielectric |
| Core Voltage | 1.2 V | — |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Configuration Interface | Serial (AS) and Parallel (PS) | — |
| Memory Interface Support | DDR, DDR2, QDRII SRAM | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Compliant | — |
| Family | — | Cyclone II |
| Embedded Memory Blocks | — | 250 M4K blocks (4 Kbit each) |
| User I/O Pins | — | 450 |
| Phase-Locked Loops (PLL) | — | 4 |
| Global Clock Networks | — | 16 |
| Core Voltage (VCCINT) | — | 1.2 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) |
| Temperature Grade | — | Commercial (0C to +85C junction) |
| Configuration Modes | — | Passive Serial (PS), Active Serial (AS), JTAG |
| Lead-Free / RoHS | — | Lead-Free / RoHS compliant per Heisener listing |