EP2C35F672C8 vs EP2C35F672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2C35F672C8 sa pamamagitan ng Altera at EP2C35F672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2C35F672C7N - 33K Logic Elements Cyclone II FPGA, 672-BGA | Altera / Intel
EP2C35F672C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP2C35F672C8 | EP2C35F672C7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | Cyclone II | Cyclone II |
| Logic Elements (LEs) | 33,216 | 33,216 |
| Total RAM Bits | 483,840 | — |
| Embedded Multipliers (18x18) | 35 | 35 |
| User I/O Pins (max) | 475 | — |
| Number of PLLs | 4 | — |
| Packhaging | 672-BGA (FineLine BGA, 1.0 mm pitch) | 672-ball FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch |
| Speed Grade | C8 (commercial, 8 ns pin-to-pin) | -7 |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Voltage (VCCINT) | 1.15 V - 1.25 V | — |
| Operating Temperature (Commercial) | 0C to +85C | — |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG | — |
| Memory Interface Support | DDR, DDR2, SDR SDRAM | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, LVDS, RSDS, mini-LVDS, PPDS | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (lead-free package) | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | — | 2,100 |
| Total Memory Bits | — | 483,840 bits |
| Phase-Locked Loops (PLLs) | — | 4 |
| User I/O Pins | — | 475 |
| I/O Banks | — | 8 |
| Core Supply Voltage | — | 1.2 V |
| Temperature na Operasyon | — | 0 °C to +85 °C (commercial) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |