EP2C35F672C8 vs EP2C35F672C7N 比較
詳細並排比較 EP2C35F672C8 由 Altera 與 EP2C35F672C7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP2C35F672C7N - 33K Logic Elements Cyclone II FPGA, 672-BGA | Altera / Intel
EP2C35F672C7N ✓ 啟用中規格比較
| 參數 | EP2C35F672C8 | EP2C35F672C7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | Cyclone II | Cyclone II |
| Logic Elements (LEs) | 33,216 | 33,216 |
| Total RAM Bits | 483,840 | — |
| Embedded Multipliers (18x18) | 35 | 35 |
| User I/O Pins (max) | 475 | — |
| Number of PLLs | 4 | — |
| 封裝 | 672-BGA (FineLine BGA, 1.0 mm pitch) | 672-ball FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch |
| Speed Grade | C8 (commercial, 8 ns pin-to-pin) | -7 |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Voltage (VCCINT) | 1.15 V - 1.25 V | — |
| Operating Temperature (Commercial) | 0C to +85C | — |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG | — |
| Memory Interface Support | DDR, DDR2, SDR SDRAM | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, LVDS, RSDS, mini-LVDS, PPDS | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant (lead-free package) | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | — | 2,100 |
| Total Memory Bits | — | 483,840 bits |
| Phase-Locked Loops (PLLs) | — | 4 |
| User I/O Pins | — | 475 |
| I/O Banks | — | 8 |
| Core Supply Voltage | — | 1.2 V |
| 工作溫度 | — | 0 °C to +85 °C (commercial) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |