EP2C35U484I8 vs EP2C35U484C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2C35U484I8 sa pamamagitan ng Altera at EP2C35U484C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2C35U484I8 | EP2C35U484C8 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Cyclone II | — |
| Logic Elements (LEs) | 33216 | — |
| Embedded Memory (bits) | 483840 | — |
| Embedded 18x18 Multipliers | 35 | — |
| Logic Array Blocks / LABs | 2076 | — |
| PLLs | 4 | — |
| Maximum User I/O | 322 | — |
| Packhaging | 484-FBGA (U484, 19x19 mm FineLine BGA) | — |
| Process Technology | 90 nm low-power CMOS | — |
| Temperature ng Junction na Operasyon | -40C to +100C (industrial) | — |
| Speed Grade | I8 (industrial, 8th speed bin) | C8 (commercial, 8th tier) |
| Configuration Modes | Passive Serial, Active Serial, JTAG | JTAG, AS, PS, FPP |
| Supply Voltage (Core) | 1.2 V | — |
| Supply Voltage (I/O Banks) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (lead-free UBGA) |
| Series | — | Cyclone II |
| Family Name | — | Cyclone II |
| Logic Elements / Cells | — | 33,216 LE |
| Total RAM Bits | — | 483,840 bits (33216 cells) |
| Number of I/O | — | 322 user I/O |
| Number of Logic Blocks/Elements | — | 2,076 logic blocks |
| Number of Gates | — | [DATA_NEEDED: equivalent gate count] |
| Number of PLLs | — | 4 |
| Embedded Multipliers | — | 35 (18x18) |
| Package Type | — | 484-FBGA (UBGA-484), lead-free |
| Package Pin Count | — | 484 balls |
| Core Voltage | — | 1.15 V to 1.25 V |
| Internal Frequency (max) | — | 500 MHz |
| Temperature na Operasyon | — | 0C to 85C (commercial) |
| Logic Family / Process | — | CMOS, 90 nm |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Katayuan ng Lifecycle | — | Not Recommended for New Designs (NRND) |