EP2C50F672C6N vs EP2C50F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2C50F672C6N sa pamamagitan ng Intel at EP2C50F672C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2C50F672C6N - 50K LE Cyclone II FPGA, 672-BGA | Intel / Altera
EP2C50F672C6N ⚠ Huling PagbiliAltera
EP2C50F672C7 - Cyclone II FPGA, 50K LE, 672-FBGA | Intel / Altera
EP2C50F672C7 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2C50F672C6N | EP2C50F672C7 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Series | Cyclone II | — |
| Number of Logic Elements (LE) | 50,528 | — |
| Number of Configurable Logic Blocks (CLB) | 3,158 | — |
| Total Embedded Memory | 594,432 bits (594 Kbits) | — |
| Number of M4K Memory Blocks | 129 | — |
| Embedded 18x18 Multipliers | 150 | 86 (150 per device family datasheet figure) |
| Number of PLLs | 4 | — |
| User I/Os | 450 | — |
| Operating Supply Voltage (Core) | 1.15 V to 1.25 V | — |
| Temperature na Operasyon | 0C to +85C (commercial junction, -C6 grade) | — |
| Speed Grade | -6 (mid-tier) | -7 |
| Packhaging | 672-ball FineLine BGA (FBGA-672), 1.0 mm pitch | 672-ball FineLine BGA (FBGA-672) |
| Uri ng Pagpapasok | Surface Mount (SMD/SMT) | — |
| Process Technology | 90 nm CMOS, low-k dielectric | 90 nm CMOS with low-k dielectric |
| Lead-Free / RoHS | Yes (LEAD FREE per datasheet) | Lead-Free / RoHS compliant per Heisener listing |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG, Fast Passive Parallel (FPP) | Passive Serial (PS), Active Serial (AS), JTAG |
| Family | — | Cyclone II |
| Logic Elements (LE) | — | 50,528 |
| Embedded Memory Bits | — | 594,432 bits |
| Embedded Memory Blocks | — | 250 M4K blocks (4 Kbit each) |
| User I/O Pins | — | 450 |
| Phase-Locked Loops (PLL) | — | 4 |
| Global Clock Networks | — | 16 |
| Core Voltage (VCCINT) | — | 1.2 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) |
| Temperature Grade | — | Commercial (0C to +85C junction) |