EP2S130F1020C3NRB vs EP2S130F1020C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S130F1020C3NRB sa pamamagitan ng Intel at EP2S130F1020C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2S130F1020C3NRB - Stratix II FPGA, 132K LE, 742 I/O, 1020-BBGA
EP2S130F1020C3NRB ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP2S130F1020C3NRB | EP2S130F1020C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Manufacturer | Intel Corporation (formerly Altera) | — |
| Series | Stratix II | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements (LEs) | 132,540 | — |
| Total Memory | 6,748 Kbits | — |
| LABs/CLBs | 6,627 | — |
| User I/O Count | 742 | — |
| Packhaging | 1020-BBGA (33x33 mm, 1.0 mm pitch) | 1020-ball FC-FBGA (33x33 mm) |
| Temperature na Operasyon | 0C to +85C (commercial, C3 speed grade) | Commercial (0C to +85C, C5 grade) |
| Process Node | 90 nm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead Free / RoHS Status | Lead Free / RoHS Compliant | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Voltage - Supply (VCCINT) | [DATA_NEEDED: VCCINT nominal] | — |
| Voltage - I/O Banks | [DATA_NEEDED: VCCIO range] | — |
| Family | — | Stratix II |
| Logic Elements | — | 132,540 |
| Adaptive Logic Modules (ALMs) | — | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | — | 6,747,840 bits |
| User I/Os | — | 734 |
| Process Technology | — | 90 nm |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Temperature Grade | — | C5 (other - per Partstack) |
| Tindminan RoHS | — | [DATA_NEEDED: rohs status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| PLLs | — | 4 (typical Stratix II feature) |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |