EP2S130F1020I4RB vs EP2S130F1020C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S130F1020I4RB sa pamamagitan ng Intel at EP2S130F1020C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2S130F1020I4RB - Stratix II FPGA 132540 Cells 1.2V FC-FBGA | Intel
EP2S130F1020I4RB ObsoletePagsanggunian na paghahambing
| Parametro | EP2S130F1020I4RB | EP2S130F1020C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Number of User I/O | 742 | — |
| Number of Logic Gates | 6,747,840 (equivalent gates) | — |
| Operating Frequency (Max) | 711.24 MHz | — |
| Process Technology | 90 nm | 90 nm |
| Core Supply Voltage | 1.2 V | — |
| Packhaging | 1020-pin FC-FBGA | 1020-ball FC-FBGA (33x33 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +100C (Industrial) | Commercial (0C to +85C, C5 grade) |
| Speed Grade | I4 | — |
| Number of Transceivers | 12 (up to 6.375 Gbps) | — |
| Embedded Memory | 6,747,840 bits (RAM blocks) | — |
| Number of PLLs | 4 (up to 16 clock pins) | — |
| Configuration Mode | JTAG / PS / PPS / EPCS / EPCQ | — |
| Level ng MSL | 3 | — |
| Tindminan RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: rohs status] |
| Adaptive Logic Modules (ALMs) | — | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | — | 6,747,840 bits |
| User I/Os | — | 734 |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Temperature Grade | — | C5 (other - per Partstack) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| PLLs | — | 4 (typical Stratix II feature) |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |