EP2S15F672C4 vs EP2S60F672C5 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2S15F672C4 sa pamamagitan ng Altera at EP2S60F672C5 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2S15F672C4 EP2S60F672C5
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Stratix II Stratix II
Logic Elements 15,600 60,440
Embedded Memory Bits 419,328 bits —
DSP Blocks 156 (approximate, per Stratix II family) 12 (dedicated 18 × 18 multipliers)
Maximum User I/Os 366 492
Packhaging 672-ball FineLine BGA (FBGA) 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch)
Process Node 90 nm —
PLLs 6 —
Temperature na Operasyon Commercial (0C to +85C, 'C' suffix) —
Speed Grade 4 —
Configuration Method Serial / Parallel (passive serial, fast passive parallel, JTAG) —
I/O Standards Supported LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance per Altera product page] Non-RoHS (legacy product, pre-RoHS production runs)
Lead-Free [DATA_NEEDED: lead-free finish status] —
Level ng MSL [DATA_NEEDED: MSL moisture sensitivity level] —
Device Family — Stratix II FPGA
Configurable Logic Blocks (CLBs) — 24,176
Total RAM Bits — 2,544,192 bits
Operating Frequency — Up to 609.76 MHz
Core Voltage — 1.2 V
Process Technology — 90 nm CMOS
Uri ng Pagpapasok — Surface Mount
Operating Temperature Grade — Commercial (C5 suffix)
Hanay ng Temperature na Operasyon — 0°C to +85°C
Number of PLLs — 4
I/O Standards — LVDS, LVTTL, SSTL, HSTL, PCI-X
Configuration Scheme — Fast Passive Parallel, JTAG, Active Serial

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita