EP2S15F672C5N vs EP2S15F672C3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S15F672C5N sa pamamagitan ng Intel at EP2S15F672C3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S15F672C5N | EP2S15F672C3 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Stratix II | Stratix II |
| Series | Altera Stratix II | — |
| Logic Elements | 15,600 | 15,600 |
| Logic Array Blocks (LABs) | 780 | — |
| Configurable Logic Blocks (CLBs) | 6,240 | — |
| Embedded Memory (bits) | 419,328 | 419,328 |
| User I/O Pins | 366 | — |
| Packhaging | 672-BBGA / FBGA-672 | 672-ball FC-FBGA |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Maximum Internal Frequency | 640 MHz | [DATA_NEEDED: max internal clock MHz] |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Speed Grade | -C5 | C3 (third commercial speed bin) |
| Lead-Free (Pb-Free) | Yes | — |
| Tindminan RoHS | RoHS Compliant | [DATA_NEEDED: RoHS compliance] |
| DSP Blocks (18-bit multipliers) | — | 156 |
| Maximum User I/O | — | 366 |
| Core Voltage | — | 1.2 V |
| Process Technology | — | 90 nm CMOS |
| Uri ng Pagpapasok | — | Surface Mount |
| Operating Temperature Grade | — | Commercial (C3 suffix) |
| PLLs | — | [DATA_NEEDED: number of PLLs] |
| Global Clock Networks | — | [DATA_NEEDED: number of global clocks] |
| Level ng MSL | — | [DATA_NEEDED: moisture sensitivity level] |