EP2S15F672C5N vs EP2S15F672C3 比較
詳細並排比較 EP2S15F672C5N 由 Intel 與 EP2S15F672C3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2S15F672C5N | EP2S15F672C3 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Stratix II | Stratix II |
| Series | Altera Stratix II | — |
| Logic Elements | 15,600 | 15,600 |
| Logic Array Blocks (LABs) | 780 | — |
| Configurable Logic Blocks (CLBs) | 6,240 | — |
| Embedded Memory (bits) | 419,328 | 419,328 |
| User I/O Pins | 366 | — |
| 封裝 | 672-BBGA / FBGA-672 | 672-ball FC-FBGA |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Maximum Internal Frequency | 640 MHz | [DATA_NEEDED: max internal clock MHz] |
| 工作溫度 | 0C to +85C (commercial) | — |
| Speed Grade | -C5 | C3 (third commercial speed bin) |
| Lead-Free (Pb-Free) | Yes | — |
| RoHS 狀態 | RoHS Compliant | [DATA_NEEDED: RoHS compliance] |
| DSP Blocks (18-bit multipliers) | — | 156 |
| Maximum User I/O | — | 366 |
| Core Voltage | — | 1.2 V |
| Process Technology | — | 90 nm CMOS |
| 安裝類型 | — | Surface Mount |
| Operating Temperature Grade | — | Commercial (C3 suffix) |
| PLLs | — | [DATA_NEEDED: number of PLLs] |
| Global Clock Networks | — | [DATA_NEEDED: number of global clocks] |
| MSL 等級 | — | [DATA_NEEDED: moisture sensitivity level] |