EP2S30F672I4 vs EP2S30F672I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S30F672I4 sa pamamagitan ng Intel at EP2S30F672I5 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S30F672I4 | EP2S30F672I5 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | Stratix II | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 33880 | — |
| Logic Array Blocks (LABs) | 1694 | — |
| Total RAM Bits | 1369728 | 1,368,576 (1.36 Mbit) |
| Number of I/O | 500 | — |
| DSP Blocks | 12 (per datasheet, family range) | 16 (9-bit x 9-bit multipliers) |
| Number of PLLs | 6 | — |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | -40C to +100C (Industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Packhaging / Kaso | 672-BBGA, FCBGA (FBGA-672) | — |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | 1.00 mm |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | [DATA_NEEDED: confirm RoHS compliance on part label] | Compliant |
| Family | — | Stratix II |
| Logic Elements (LE) | — | 33,880 |
| Adaptive Logic Modules (ALM) | — | 13,567 (approx., per Stratix II family ratio) |
| Maximum User I/Os | — | 500 (492 outputs reported) |
| Maximum Operating Frequency | — | 609.76 MHz |
| Core Supply Voltage | — | 1.2 V |
| I/O Supply Voltage | — | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Packhaging | — | 672-ball FC-FBGA (FineLine BGA) |
| Lead-Free | — | Yes |
| Speed Grade | — | 5 (fast) |