EP2S30F672I4N vs EP2S30F672C4N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2S30F672I4N sa pamamagitan ng Altera at EP2S30F672C4N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2S30F672I4N EP2S30F672C4N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Stratix II —
Logic Elements (LEs) 33,880 —
Logic Array Blocks (LABs) 1,694 —
Total RAM Bits 1,369,728 1,369,728
Maximum User I/Os 500 —
Packhaging 672-BBGA, FCBGA (27x27 mm) 672-BBGA, FCBGA (FineLine BGA)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon -40C to +100C (industrial) 0C to +85C (Commercial, C4 grade)
Core Supply Voltage 1.15 V to 1.25 V —
Technology Node 90 nm —
Speed Grade I4 (speed grade 4, industrial) C4 (Commercial, internal performance bin 4)
Volte ng Pagbibigay 1.15 V to 1.25 V —
Maximum Frequency 711.24 MHz —
Level ng MSL 3 (per JEDEC J-STD-020) 3 (168 hours)
Tindminan RoHS Compliant [DATA_NEEDED: rohs status]
Series — Stratix II
Logic Elements — 33,880
Number of LABs/CLBs — 1694
Number of I/O — 500
Core Voltage — 1.2 V
Process Technology — 90 nm CMOS
Maximum Internal Frequency — 711.24 MHz
Lead-Free / Halogen-Free — [DATA_NEEDED: lead-free / halogen-free status]
Embedded Multipliers / DSP Blocks — [DATA_NEEDED: DSP block count]
Transceivers — N/A (Stratix II non-GX variant)
Configuration Method — Passive serial / Fast passive parallel / JTAG

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