EP2S60F484I4N vs EP2S60F484C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S60F484I4N sa pamamagitan ng Intel at EP2S60F484C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S60F484I4N | EP2S60F484C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | Stratix II | — |
| Family | Stratix II (EP2S60) | Stratix II |
| Logic Elements (LE) | 60,440 | — |
| Logic Array Blocks (LABs) | 3,022 | — |
| Total RAM Bits | 2,544,192 | — |
| Number of I/O | 334 | — |
| Number of DSP Blocks | 18 (typical) | — |
| Number of PLLs | 12 (typical) | — |
| Packhaging | 484-BBGA, FCBGA | 484-BGA (F484), 1.0 mm pitch |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | -40C to +100C (Industrial, I4) | — |
| Speed Grade | -4 (mid) | -3 (fastest commercial) |
| Volte ng Pagbibigay | 1.2 V (core) | — |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| Logic Elements | — | 60,440 |
| Adaptive LUTs (ALUTs) | — | 48,352 |
| Embedded Memory (TriMatrix) | — | 2,544 Kbits (M4K + M512 + M-RAM) |
| Embedded DSP Blocks | — | 12 (48 GMACs at 450 MHz) |
| Maximum User I/O Pins | — | 334 |
| Process Technology | — | 90 nm CMOS, 1.2 V core |
| Operating Temperature (Commercial) | — | 0C to +85C (TJ) |
| Supply Voltage VCCINT | — | 1.2 V nominal |
| Configuration Modes | — | FPP, AS, PS, JTAG |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |