EP2SGX130GF40C3N vs EP2SGX130GF40C3NES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX130GF40C3N sa pamamagitan ng Intel at EP2SGX130GF40C3NES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2SGX130GF40C3NES - Stratix II GX FPGA, 132K LE, 6.375Gbps | Altera
EP2SGX130GF40C3NES ObsoletePagsanggunian na paghahambing
| Parametro | EP2SGX130GF40C3N | EP2SGX130GF40C3NES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix II GX | Stratix II GX |
| Logic Elements | 132,540 | 132540 |
| Embedded Memory | 6.7 Mbits | — |
| Embedded Multipliers (18x18) | 252 | — |
| User I/O Count | 734 | — |
| Transceiver Count | 40 channels | — |
| Max Transceiver Data Rate | 6.375 Gbps | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Packhaging | 1508-ball FC-FBGA | 1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch) |
| Uri ng Pagpapasok | Surface Mount (flip-chip BGA) | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Speed Grade | C3 | — |
| Configuration Mode | Passive Serial / Fast Passive Parallel / JTAG | — |
| Tindminan RoHS | Compliant | Lead-free compliant (per package code MS-034AAU-1) |
| Logic Array Blocks (LABs) | — | 7047 |
| Maximum Internal Frequency | — | 778.82 MHz |
| Transceiver Channels | — | 4 to 20 (per device family configuration) |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Transceiver Feature | — | Embedded SERDES with Clock/Data Recovery (CRU) |
| Uri ng Memory | — | TriMatrix embedded memory (distributed RAM, block RAM, shift register) |
| Operating Temperature Grade | — | Commercial Extended |
| Terminal Form | — | Ball (BGA) |
| Series | — | EP2SGX130 |