EP2SGX130GF40C3N vs EP2SGX130GF40C3NES 比較
詳細並排比較 EP2SGX130GF40C3N 由 Intel 與 EP2SGX130GF40C3NES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP2SGX130GF40C3NES - Stratix II GX FPGA, 132K LE, 6.375Gbps | Altera
EP2SGX130GF40C3NES Obsolete規格比較
| 參數 | EP2SGX130GF40C3N | EP2SGX130GF40C3NES |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Stratix II GX | Stratix II GX |
| Logic Elements | 132,540 | 132540 |
| Embedded Memory | 6.7 Mbits | — |
| Embedded Multipliers (18x18) | 252 | — |
| User I/O Count | 734 | — |
| Transceiver Count | 40 channels | — |
| Max Transceiver Data Rate | 6.375 Gbps | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| 封裝 | 1508-ball FC-FBGA | 1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch) |
| 安裝類型 | Surface Mount (flip-chip BGA) | Surface Mount |
| 工作溫度 | 0C to +85C (commercial) | — |
| Speed Grade | C3 | — |
| Configuration Mode | Passive Serial / Fast Passive Parallel / JTAG | — |
| RoHS 狀態 | Compliant | Lead-free compliant (per package code MS-034AAU-1) |
| Logic Array Blocks (LABs) | — | 7047 |
| Maximum Internal Frequency | — | 778.82 MHz |
| Transceiver Channels | — | 4 to 20 (per device family configuration) |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Transceiver Feature | — | Embedded SERDES with Clock/Data Recovery (CRU) |
| 記憶體類型 | — | TriMatrix embedded memory (distributed RAM, block RAM, shift register) |
| Operating Temperature Grade | — | Commercial Extended |
| Terminal Form | — | Ball (BGA) |
| Series | — | EP2SGX130 |