EP2SGX130GF40C3NES vs EP2SGX90EF35C3NES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX130GF40C3NES sa pamamagitan ng Altera at EP2SGX90EF35C3NES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2SGX130GF40C3NES - Stratix II GX FPGA, 132K LE, 6.375Gbps | Altera
EP2SGX130GF40C3NES ObsoletePagsanggunian na paghahambing
| Parametro | EP2SGX130GF40C3NES | EP2SGX90EF35C3NES |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix II GX | Stratix II GX |
| Logic Elements | 132540 | 90,000 |
| Logic Array Blocks (LABs) | 7047 | — |
| Maximum Internal Frequency | 778.82 MHz | — |
| Process Technology | 90 nm CMOS | — |
| Core Voltage | 1.2 V | — |
| Transceiver Channels | 4 to 20 (per device family configuration) | 4 to 20 |
| Maximum Transceiver Data Rate | 6.375 Gbps | — |
| Transceiver Feature | Embedded SERDES with Clock/Data Recovery (CRU) | — |
| Uri ng Memory | TriMatrix embedded memory (distributed RAM, block RAM, shift register) | — |
| Packhaging | 1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch) | — |
| Operating Temperature Grade | Commercial Extended | Commercial Extended |
| Terminal Form | Ball (BGA) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Lead-free compliant (per package code MS-034AAU-1) | [DATA_NEEDED: rohs] |
| Series | EP2SGX130 | — |
| Number of Terminals | — | 35 |
| Package Type | — | BGA |
| Package Shape | — | Square |
| Form of Terminal | — | Ball |
| Core Supply Voltage | — | 1.2 V |
| Transceiver Data Rate (max) | — | 6.375 Gbps |
| Process Node | — | 90 nm |
| Logic Element | — | ALM (Adaptive Logic Module) |
| Configuration Interface | — | JTAG / Passive Serial / Active Serial |
| Embedded Memory Type | — | TriMatrix |
| Lead Free | — | [DATA_NEEDED: lead_free] |